Electrical Characterization of Mesh-Structured Floating-Gate Neuromorphic Transistors with Varying Mesh Sizes
Abstract
This study investigates the influence of mesh-structured floating-gate (FG) geometry on the electrical and DC synaptic characteristics of flash-memory-based neuromorphic transistors. Devices with mesh sizes of 3 µm × 3 µm, 1 µm × 1 µm, 500 nm × 500 nm, and 200 nm × 200 nm were comparatively evaluated while maintaining the same channel dimensions. As the mesh size decreased, the perimeter-to-area (P/A) ratio increased from 1.33 to 20.0 µm-1, and the cycle-averaged memory window increased from 0.86 to 1.68 V under the same DC program/erase sequence. The 200 nm device also exhibited a read-current modulation range exceeding six orders of magnitude, compared with approximately three orders of magnitude for the 3 µm device. These trends are consistent with a greater contribution of mesh-edge regions to local electrostatic conditions and charge injection. At the same time, smaller mesh sizes produced more abrupt threshold-voltage and read-current changes during the initial program/erase steps, indicating a trade-off between response sensitivity and gradual state modulation. These results show that mesh-size scaling provides an effective geometrical design variable for tuning the memory window and readout characteristics of mesh-structured floating-gate synaptic transistors.
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