A hardware-grounded energy taxonomy for comparing deep and Spiking Neural Network inference on edge platforms
Abstract
Energy consumption is becoming one of the main constraints for neural network inference on edge devices, where compute, memory, and power budgets are tight. A large number of works already study the efficiency of Deep Neural Networks (DNNs), and a growing body of work does the same for Spiking Neural Networks (SNNs). However, comparing the two on equal terms is not straightforward because existing analyses rarely rely on a shared decomposition of inference energy linked to the actual hardware behavior. This Mini Review synthesizes hardware-aware studies into a unified taxonomy that decomposes inference energy into seven contributions: computation E compute , memory access E memory , internal state E state , temporal processing E temporal , activation E activation , static leakage E leakage , and clock distribution E clock . The corresponding expressions are derived from classical CMOS energy models and interpreted using representative findings from hardware studies. We illustrate the taxonomy using representative studies on microcontrollers, FPGAs, ASICs, and neuromorphic processors. The objective is not to recommend one paradigm. It is to provide a reading grid close to the hardware that can support architectural choices when energy, accuracy, and latency cannot all be optimized at once.
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